The present invention relates to an integrated circuit device, an electro-optical device, an electronic instrument, and the like.
As an electro-optical panel used for electronic instruments (e.g., portable telephone, television, and projector (projection-type display device)), a simple matrix type liquid crystal panel, an active matrix type liquid crystal panel that utilizes a switch element (e.g., thin film transistor), and the like have been known. An electro-optical panel that utilizes a light-emitting element such as an electroluminescence (EL) element has also attracted attention.
In recent years, the number of data lines (source lines) of an electro-optical panel has increased along with an increase in the screen size and the number of pixels of an electro-optical panel. On the other hand, an increase in accuracy of a voltage applied to each data line has been desired. A reduction in power consumption and chip size of a data driver (source driver) that drives data lines of an electro-optical panel has also been desired along with a demand for a reduction in power consumption and weight and size of electronic instruments provided with an electro-optical panel.
For example, JP-A-2005-175811 and JP-A-2005-175812 disclose a configuration that enables a rail-to-rail operation of an output circuit of a data driver that drives a data line while supplying a voltage to the data line with high accuracy.
According to the technologies disclosed in JP-A-2005-175811 and JP-A-2005-175812, the rail-to-rail operation is implemented by controlling the drive capability by providing an auxiliary circuit in each output circuit. Therefore, the circuit scale of the data driver increases due to the addition of the auxiliary circuits Moreover, the transistor size must be increased in order to suppress a variation in voltage applied to the data line. As a result, the chip size increases.
JP-A-2007-243125 discloses a layout method that reduces the chip size by adjacently disposing a data driver block and a memory block along the long side direction of an integrated circuit device.
However, a reduction in chip size and an increase in display characteristics cannot be sufficiently achieved by this layout method.